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copyright ? cirrus logic, inc. 2006 (all rights reserved) http://www.cirrus.com cs5371a cs5372a low-power, high-performance ? modulators features ? fourth-order ? architecture ? clock-jitter-tolerant architecture ? input voltage: 5 v pp fully differential ? input signal band width: dc to 2 khz ? high dynamic range ? 127 db snr @ 215 hz bw (2 ms sampling) ? 124 db snr @ 430 hz bw (1 ms sampling) ? low total harmonic distortion ? -118 db thd typical (0.000126%) ? -112 db thd maximum (0.000251%) ? low power consumption ? normal operation: 25 mw per channel ? power down: 10 w per channel ? small footprint, 24-pin ssop package ? multi-channel system support ? 1-channel system: cs5371a ? 2-channel system: cs5372a ? 3-channel system: cs5371a + cs5372a ? 4-channel system: cs5372a + cs5372a ? bipolar power supply configuration ? va+ = +2.5 v; va- = -2.5 v; vd = +3.3 v description the cs5371a and cs5372a are one- and two-channel, high-dynamic-range, fourth-order ? modulators intend- ed for geophysical and sonar applications. when combined with cs3301a / cs330 2a differential amplifi- ers, the cs4373a test dac and cs5376a digital filter, a small, low-power, self-testing, high-accuracy, multi- channel measurement system results. the modulators have high dynamic range and low total harmonic distortion with very low power consumption. they convert differential analog input signals from the cs3301a / cs3302a amplifiers to an oversampled seri- al bit stream at 512 kbits pe r second. this oversampled bit stream is then decimated by the cs5376a digital filter to a 24-bit output at the selected output word rate. in normal operation, power consumption is 5 ma per channel. each modulator can be independently powered down to 500 a per channel, and by halting the input clock they will enter a micro- power state using only 2 a per channel. the cs5371a and cs5372a modulators are available in small 24-pin ssop packages, providing exceptional per- formance in a very small footprint. ordering in formation see page 31 . clock generator inf1+ vref+ vref- va+ va- vd gnd pwdn1 mflag1 mdata1 mclk msync mflag2 mdata2 pwdn2 inf1- inr1- inr1+ inf2+ inf2- inr2- inr2+ 4th order ? modulator 4th order ? modulator ofst cs5372a clock generator inf+ vref+ vref- va+ va- vd gnd pwdn mflag mdata mclk msync inf- inr- inr+ 4th order ? modulator ofst cs5371a dec ?06 ds748f1
cs5371a cs5372a 2 ds748f1 table of contents 1. characteristics and specifications ........................................................................ 4 specified operating conditions . .............. ................ ............. ............. ............. ........... 4 absolute maximum ratings ......... ................ ................ ............. ............. ............. ........... 4 temperature conditions ............................................................................................... 5 analog input characteristics ................................................................................... 5 performance characteristics ................................................................................... 7 performance plots ......................................................................................................... 9 digital characteristics .............................................................................................. 10 power supply characteristics ................................................................................ 13 2. system diagram ......................................................................................................... ... 14 3. modulator operation ................................................................................................... 15 3.1 one?s density ............................................................................................................. ...... 15 3.2 decimated 24-bit output .................................................................................................. 1 6 3.3 synchronization ........................................................................................................... .... 16 3.4 idle tones ................................................................................................................ ........ 16 3.5 stability ................................................................................................................. ........... 16 4. analog signals ............................................................................................................ .... 17 4.1 inr, inf modulator inputs ..................... ...................................................................... 17 4.2 input impedance ........................................................................................................... ... 17 4.3 anti-alias filter ......................................................................................................... ........ 18 4.4 analog differential signals ............................................................................................... 18 5. digital signals ........................................................................................................... ...... 19 5.1 mclk connection ........................................................................................................... .19 5.2 msync connection ......................................................................................................... 1 9 5.3 mdata connection ......................................................................................................... 2 0 5.4 mflag connection ......................................................................................................... 2 0 5.5 ofst connection ........................................................................................................... .20 6. power modes ............................................................................................................... ...... 21 6.1 normal operation .......................................................................................................... ... 21 6.2 power down, mclk enabled .......................................................................................... 21 6.3 power down, mclk disabled .......................................................................................... 21 7. voltage reference ........................................................................................................ 2 2 7.1 vref power supply ........................................................................................................ 2 2 7.2 vref rc filter ............................................................................................................ .... 22 7.3 vref pcb routing .......................................................................................................... 22 7.4 vref input impedance .................................................................................................... 22 7.5 vref accuracy ............................................................................................................. ... 23 8. power supplies ............................................................................................................ .... 24 8.1 power supply bypassing ................................................................................................. 24 8.2 pcb layers and routing ................................................................................................. 24 8.3 power supply rejection ................................................................................................... 2 4 8.4 scr latch-up considerations ......................................................................................... 25 8.5 dc-dc converters .......................................................................................................... .25 9. pin description - cs5371a ............................................................................................. 26 10. pin description - cs5372a ........................................................................................... 28 11. package dimensions ..................................................................................................... 30 12. ordering information ................................................................................................ 31 13. environmental, manufacturing, & ha ndling information .......................... 31 14. revision history ........................................................................................................ ... 31
cs5371a cs5372a ds748f1 3 list of figures figure 1. anti-alias filter components............. ............................................................................ ... 6 figure 2. modulator noise perf ormance ......................................................................................... 9 figure 3. modulator + cs4373a test dac dynami c performance ................................................ 9 figure 4. digital input rise and fall times ................................................................................... 1 0 figure 5. digital output rise and fall times ...... .......................................................................... 10 figure 6. system timing diagram.................... ............................................................................ .12 figure 7. mclk / msync timing detail ............. .......................................................................... 12 figure 9. connection diagram ................................................................................................... ... 14 figure 8. system block diagram ................................................................................................. .. 14 figure 10. cs5371a and cs5372a block diagrams .................................................................... 15 figure 11. analog signals ...................................................................................................... ....... 17 figure 12. digital signals ..................................................................................................... ......... 19 figure 13. power mode diagram .................................................................................................. 21 figure 14. voltage reference circuit .................. ......................................................................... .22 figure 15. power supply diagram ................................................................................................ 24 list of tables table 1. 24-bit output coding for the cs5371a an d cs5372a modulator and cs 5376a digital filter com- bination ....................................................................................................................... .. 16
cs5371a cs5372a 4 ds748f1 1. characteristics an d specifications ? min / max characteristics and spec ifications are gu aranteed over the specified operating conditions . ? typical performance characteristics and specificatio ns are measured at nominal supply voltages and t a = 25 c. ? gnd = 0 v. single-ended voltages with respect to gnd, differential voltages with respect to opposite half. ? device is connected as shown in figure 9 on page 14 unless otherwise noted. specified operating conditions notes: 1. va- must always be the most-negative input vo ltage to avoid potential scr latch-up conditions. 2. by design, a 2.500 v voltage reference input results in the best si gnal-to-noise performance. 3. channel-to-channel gain accuracy is directly propor tional to the voltage reference absolute accuracy. 4. vref inputs must satisfy: va- vref- < vref+ va+. absolute maximum ratings warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not gu aranteed at these extremes. notes: 5. transient currents up to 100 ma will not cause scr latch-up. 6. includes continuous over-voltage condit ions at the modulator analog input pins. parameter symbol min nom max unit bipolar power supplies positive analog 2% va+ 2.45 2.50 2.55 v negative analog ( note 1 ) 2% va- -2.45 -2.50 -2.55 v positive digital 3% vd 3.20 3.30 3.40 v voltage reference [vref+] - [vref-] ( note 2, 3 ) vref - 2.500 - v vref- ( note 4 )vref- - va- - v thermal ambient operating temperature industrial (-isz) t a -40 25 85 c parameter symbol min max parameter dc power supplies positive analog negative analog digital va+ va- vd -0.5 -6.8 -0.5 6.8 0.5 6.8 v v v analog supply differential (va+) - (va-) va diff -6.8v digital supply differential (vd) - (va-) vd diff -6.8v input current, power supplies ( note 5 )i pwr -50ma input current, any pin except supplies ( note 5, 6 )i in -10ma output current ( note 5 )i out -25ma power dissipation pdn - 500 mw analog input voltages v ina (va-) - 0.5 (va+) + 0.5 v digital input voltages v ind -0.5 (vd) + 0.5 v storage temperature range t stg -65 150 oc
cs5371a cs5372a ds748f1 5 temperature conditions analog input characteristics notes: 7. maximum integrated noise over the measurement bandwidth for the voltage reference device attached to the vref inputs. 8. anti-alias capacitors are discrete external component s and must be of good quality (c0g, npo, poly). poor quality capacitors will degrade total harmonic distor tion (thd) performance. see figure 1 on page 6 parameter symbol min typ max unit ambient operating temperature t a -40 - 85 oc storage temperature range t str -65 - 150 oc allowable junction temperature t jct --125oc junction to ambient thermal impedance (4-layer pcb) ja -65-oc/w parameter symbol min typ max unit vref input [vref+] - [vref-] ( note 2, 3 ) vref - 2.500 - v vref- ( note 4 )vref- - va- - v vref input current vref imod -120- a vref input noise ( note 7 )vref in --1v rms modulator inr , inf inputs external anti-alias filter series resistance ( note 8 ) differential capacitance r aa c diff - - 680 20 - - ? nf differential input impedance inr inf zdif inr zdif inf - - 20 1 - - k ? m ? single-ended input impedance inr inf zse inr zse inf - - 40 2 - - k ? m ?
cs5371a cs5372a 6 ds748f1 cs5371a / cs5372a modulator inr+ inf+ inf- inr- 20nf c0g 20nf c0g 680 cs3301a / cs3302a amplifier outr+ outf+ outf- outr- 680 680 680 cs5371a / cs5372a modulator inr+ inf+ inf- inr- 20nf c0g 20nf c0g 0 cs3301 / cs3302 amplifier outr+ outf+ outf- outr- 0 0 0 figure 1. anti-alias filter components
cs5371a cs5372a ds748f1 7 performance characteristics notes: 9. guaranteed by design and/or characterization. 10. the upper bandwidth limit is determined by the digital filter cut-off frequency. 11. common mode voltage is defined as the mid-point of the differential signal. 12. dynamic range defined as 20 log [ (rms full scale) / (r ms idle noise) ] where idle noise is measured from a cs3301a / cs3302a amplifier terminated input at 1x gain. 13. signal-dependent noise defined as 20 log [ (rms fu ll scale) / (rms signal noise) ] where signal noise is measured by subtracting out the signal po wer at the fundamental and harmonic frequencies. 14. tested with a 31.25 hz sine wave at -1 db amplitude. parameter symbol min typ max unit signal characteristics input signal frequencies ( note 9, 10) v bw dc - 2000 hz full-scale differential ac input ( note 9 )v ac --5v pp full-scale differential dc input ( note 9 )v dc -2.5 - 2.5 v input common mode voltage ( note 11) v cm - (va-)+2.5 -v input voltage range (v cm signal) ( note 9) v rng (va-)+0.7 - (va+)-1.25 v dynamic performance dynamic range (1/4 ms) dc to 1720 hz ( note 10, 12 ) (1/2 ms) dc to 860 hz (1 ms) dc to 430 hz (2 ms) dc to 215 hz (4 ms) dc to 108 hz (8 ms) dc to 54 hz (16 ms) dc to 27 hz snr - - 121 - - - - 109 121 124 127 130 133 136 - - - - - - - db db db db db db db signal-dependent noise (1 ms) dc to 430 hz ( note 13, 14 ) sdn 100 110 - db total harmonic distortion ( note 14 ) thd - -118 -112 db linearity ( note 14 )lin - 0.000126 0.000251 % common mode rejection ratio cmrr - 110 - db channel crosstalk (cs5372a only) cxt - -150 - db
cs5371a cs5372a 8 ds748f1 performance characteristics (cont.) notes: 15. specification is for the parameter over the specif ied temperature range and is for the device only. it does not include the effects of external components. 16. specification applies to the effective offset voltage ca lculated from the output co des of the digital filter following offset calibra tion and correction. 17. offset calibration is performed in the digita l filter and includes the full-scale signal range. parameter symbol min typ max unit gain accuracy channel to channel gain accuracy ( note 3 ) ga - 1 2 % channel gain drift ( note 15 )ga tc - 22 - ppm/c offset offset voltage, differential (ofst = 0) ofst - 1 - mv offset voltage, cs5371a (ofst = 1) ofst - -60 - mv offset voltage, cs5372a channel 1 (ofst = 1) ofst - -60 - mv offset voltage, cs5372a channel 2 (ofst = 1) ofst - -35 - mv offset after calibration ( note 16 )ofst cal -1- v offset calibration range ( note 17 )ofst rng -100- %fs offset voltage drift ( note 15 )ofst tc -300- nv/c
cs5371a cs5372a ds748f1 9 performance plots figure 2. modulator noise performance figure 3. modulator + cs4373a test dac dynamic performance
cs5371a cs5372a 10 ds748f1 digital characteristics notes: 18. device is intended to be driven with cmos logic levels. parameter symbol min typ max unit digital inputs high-level input voltage ( note 9, 18 )v ih 0.6*vd - vd v low-level input voltage ( note 9, 18 )v il 0.0 - 0.8 v input leakage current i in -110 a digital input capacitance (note 9) c in -9- pf input rise times except mclk (note 9) t rise --100ns input fall times except mclk (note 9) t fall --100ns digital outputs high-level output voltage, i out =-40 a( note 9 )v oh vd - 0.3 - - v low-level output voltage, i out =40 a( note 9 )v ol --0.3v high-z leakage current i oz --10 a digital output capacitance (note 9) c out -9- pf output rise times (note 9) t rise --100ns output fall times (note 9) t fall --100ns 0.9 * vd 0.1 * vd t fall t rise figure 4. digital input rise and fall times 0.9 * vd 0.1 * vd t fall t rise figure 5. digital output rise and fall times
cs5371a cs5372a ds748f1 11 digital characteristics (cont.) notes: 19. mclk is generated by the digital filter. if mclk is disabled, the device automatically enters a power- down state. 20. msync is generated by the digital filter and is latched on mclk falling edge, synchronization instant ( t 0 ) is on the next mclk rising edge. 21. decimated, filtered, and offs et-corrected 24-bit output word from the digital filter. parameter symbol min typ max unit master clock input mclk frequency ( note 19 )f clk -2.048- mhz mclk period ( note 19 )t mclk -488- ns mclk duty cycle ( note 9 )mclk dc 40 - 60 % mclk rise time ( note 9 )t rise --50ns mclk fall time ( note 9 )t fall --50ns mclk jitter (in-band or aliased in-band) ( note 9 )mclk ibj --300ps mclk jitter (out-of-band) ( note 9 )mclk obj --1 ns master sync input msync setup time to mclk falling ( note 9, 20 )t mss 20 122 - ns msync period ( note 9, 20 )t msync 40 976 - ns msync hold time after mclk falling ( note 9, 20 )t msh 20 122 - ns mdata output mdata output bit rate f mdata - 512 - kbits/s mdata output bit period t mdata - 1953 - ns mdata output one?s density range ( note 9 )mdat od 14 - 86 % full-scale output code ( note 21 )mdat fs 0xa2ebe0 - 0x5d1420
cs5371a cs5372a 12 ds748f1 digital characteristics (cont.) mclk msync t mdata tdata 0 (2.048 mhz) (512 khz) (256 khz) sync mflag figure 6. system timing diagram mclk msync t 0 (2.048 mhz) t mss t mclk t msync t msh mdata (512 khz) mflag t mdata figure 7. mclk / msync timing detail
cs5371a cs5372a ds748f1 13 power supply characteristics notes: 22. all outputs unloaded. digital inpu ts forced to vd or gnd respectively. 23. power supply rejection is characterized by appl ying a 100 mvp-p 50 hz sine wave to each supply. parameter symbol min typ max unit power supply current, cs5371a analog power supply current ( note 22 )i a -56 ma digital power supply current ( note 22 )i d -75125 a power supply current, cs5372a ch1 + ch2 analog power supply current ( note 22 )i a -911ma digital power supply current ( note 22 )i d -75125 a power supply current, cs5372a ch1 or ch2 only analog power supply current ( note 22 )i a -56 ma digital power supply current ( note 22 )i d -75125 a power down current, mclk enabled analog power supply current ( note 22 )i a -0.5- ma digital power supply current ( note 22 )i d -75- a power down current, mclk disabled analog power supply current ( note 22 )i a -1- a digital power supply current ( note 22 )i d -1- a power down timing (after mclk disabled) ( note 9 )pd tc -40- s power supply rejection power supply rejection ratio ( note 23 ) psrr - 100 - db
cs5371a cs5372a 14 ds748f1 2. system diagram cs5372a ? modulator inf+ inr+ inf- inr- inf- inr- inf+ inr+ vref+ vref- va+ va- vd gnd mdata1 mflag1 mdata2 mflag2 mclk msync pwdn1 ofst pwdn2 vref 2.5 v va+ va- 10 ? 0.01 f vd cs5376a digital filter vdd2 gnd mdata1 mflag1 mdata2 mflag2 mclk msync gpio gpio gpio va+ 0.1 f 0.01 f vd va- 0.1 f 20nf c0g 20nf c0g 680 cs3301a cs3302a amplifier outr+ outf+ outf- outr- 680 680 680 20nf c0g 20nf c0g 680 cs3301a cs3302a amplifier outr+ outf+ outf- outr- 680 680 680 va+ va+ va- va- va+ va+ va- va- 100 f figure 9. connection diagram differential sensor differential sensor differential sensor differential sensor ? modulator cs5371a ? modulator cs5371a digital filter cs5376a test dac controller or configuration eeprom system telemetry amp m u x cs3301a cs3302a amp m u x amp m u x amp m u x cs4373a cs3301a cs3302a cs3301a cs3302a cs3301a cs3302a cs5372a cs5372a figure 8. system block diagram
cs5371a cs5372a ds748f1 15 3. modulator operation the cs5371a and cs5372a are one- and two-channel, fourth-order ? modulators opti- mized for extremely hi gh-resolution measure- ment of signals between dc and 2000 hz. when combined with cs 3301a / cs3302a dif- ferential amplifiers, the cs4373a test dac and cs5376a digital filter , a small, low-power, self-testing, high-a ccuracy, multi-channel measurement system results. the cs5371a and cs5372a modulators have high dynamic range and low total harmonic distortion with very low power consumption and are optimized for extremely high-resolu- tion measurement of 5 v p-p or smaller differen- tial signals. they c onvert analog input signals from the cs3301a / cs3302a differential am- plifiers to an oversampl ed serial bit stream at 512 kbits per second which is then passed to the digital filter. the companion cs5376a di gital filter gener- ates the clock and sync hronization inputs for the cs5371a / cs5372a modulators while re- ceiving the one-bit data and over-range flag outputs. the digital filt er decimates the modu- lator?s oversampled outp ut bit stream to a high-resolution, 24-bit output at the selected output word rate. 3.1 one?s density in normal operation a differential analog input signal is converted to an oversampled ? seri- al bit stream on the mdata output, with a one?s density proportional to the differential amplitude of the analog input signal. one?s density of the md ata output is defined as the ratio of ?1? bits to total bits in the serial bit stream output, i.e. an 86% one?s density has, on average, a ?1? va lue in 86 of every 100 output data bits. th e mdata output has a nominal 50% one?s densit y for a mid-scale dif- ferential input, approximately 86% one?s den- sity for a positive full-scale input signal, and approximately 14% one?s density for a nega- tive full-scale input signal. clock generator inf1+ vref+ vref- va+ va- vd gnd pwdn1 mflag1 mdata1 mclk msync mflag2 mdata2 pwdn2 inf1- inr1- inr1+ inf2+ inf2- inr2- inr2+ 4th order ? modulator 4th order ? modulator ofst cs5372a clock generator inf+ vref+ vref- va+ va- vd gnd pwdn mflag mdata mclk msync inf- inr- inr+ 4th order ? modulator ofst cs5371a figure 10. cs5371a and cs5372a block diagrams
cs5371a cs5372a 16 ds748f1 3.2 decimated 24-bit output when the cs5371a and cs5372a modulator operates with the cs5376a digital filter, the fi- nal decimated, 24-bit, full-scale output code range depends if digital offset correction is en- abled. with digital offset correction enabled within the digital filter, amplifier offset and the modulator internal offset are removed from the final conversion result. 3.3 synchronization the modulator is desi gned to operate synchro- nously with other modul ators in a distributed measurement network, so a rising edge on the msync input resets t he internal conversion state machine to synchronize analog sample timing. msync is autom atically generated by the cs5376a digita l filter after receiving a syn- chronization signal from the external system, and is chip-to-chip accurate within 1 mclk period. 3.4 idle tones the cs5371a and cs5372a are delta-sigma- type modulators and so can produce ?idle tones? in the measur ement bandwidth when the differential input signal is a steady-state dc signal near mid-sca le. idle tones result from low-frequency patterns in the output data stream and appear in t he measurement spec- trum as small tones about -135 db down from full scale. if the ofst pin is pulled high, idle tones are eliminated within the modulator by adding -60 mv (channel 1 of cs5371a and cs5372a) or -35 mv (channel 2 of cs5372a) of internal differential offset duri ng conversion to push idle tones out of the measurement bandwidth. care should be taken to ensure external offset voltages do not negate the internally added differential offset, or id le tones will re-appear. 3.5 stability the cs5371a and cs5372a ? modulators have a fourth-order architecture which is con- ditionally stable and may go into an oscillatory condition if the analog in puts are over-ranged more than 5% past eit her positive or negative full scale. if an unstable condition is detected, the modu- lator collapses to a first-order system and tran- sitions the mflag output low-to-high to signal an error condition to the cs5376a digital filter. the analog input signal must be reduced to within the full-scale range for at least 32 mclk cycles for the modulator to recover from an os- cillatory condition. if the analog input remains over-ranged for an extend ed period, the mod- ulator will cycle between fourth-order and first- order operation and the mflag output will be seen to pulse. table 1. 24-bit output coding for the cs5371a and cs5372a modulator and cs5376a digital filter combination modulator differential analog input signal cs5376a digital filter 24-bit output code offset corrected -60 mv offset -35 mv offset > + (vref+5%) error flag possible + vref 5d1420 5ad840 5bc688 0 v 000000 fdc420 feb268 - vref a2ebe0 a527c0 a43978 > - (vref+5%) error flag possible
cs5371a cs5372a ds748f1 17 4. analog signals the cs5371a and cs5372a modulators have differential analog inpu ts which are separated into rough and fine charge differential pairs (inr, inf) to maximi ze sampling accuracy. both sets of modulator inputs require a simple differential anti-alias rc filter to ensure high- frequency signals do not alias into the mea- surement bandwidth. 4.1 inr, inf modulator inputs the modulator analog inputs are separated into differential r ough and fine signals (inr, inf). the positive half of the differential input signal is connected to inr+ and inf+, while the negative half is attached to inf- and inr-. the inr pins are sw itched-capacitor ?rough charge? inputs that pr e-charge the internal an- alog sampling capacitor before it is connected to the inf fine input pins. 4.2 input impedance the modulator inputs have a dynamic switched-capacitor archit ecture and so have a rough charge input impedance that is inversely proportional to the input master clock frequen- cy and the input capacit or size, [1 / (f x c)]. internal to the modulator, the rough inputs (inr) pre-charge t he sampling capacitor used by the fine inputs (inf), therefore the in- put current to the fine inputs is typically very low and the effective input impedance is or- ders of magnitude above the impedance of the rough inputs. cs5372a ? modulator inf+ inr+ inf- inr- inf- inr- inf+ inr+ vref+ vref- va+ va- vd gnd mdata1 mflag1 mdata2 mflag2 mclk msync pwdn1 ofst pwdn2 vref 2.5 v va+ va- 10 ? 0.01 f vd cs5376a digital filter vdd2 gnd mdata1 mflag1 mdata2 mflag2 mclk msync gpio gpio gpio va+ 0.1 f 0.01 f vd va- 0.1 f 20nf c0g 20nf c0g 680 cs3301a cs3302a amplifier outr+ outf+ outf- outr- 680 680 680 20nf c0g 20nf c0g 680 cs3301a cs3302a amplifier outr+ outf+ outf- outr- 680 680 680 va+ va+ va- va- va+ va+ va- va- 100 f figure 11. analog signals ? mclk = 2.048 mhz ? inr internal input capacitor = 20 pf ? impedance = [1 / (2.048 mhz * 20 pf)] = 24 k ? .
cs5371a cs5372a 18 ds748f1 4.3 anti-alias filter the modulator inputs are required to be band- width limited to ensure modulator loop stability and prevent high-frequen cy signals from alias- ing into the measurem ent bandwidth. the use of simple, single-pole, differential, low-pass rc filters across the in r and inf inputs en- sures high-frequency si gnals are rejected be- fore they can alias into the measurement bandwidth. the cs3301a / cs3302a differential amplifi- ers are designed with s eparate rough and fine analog outputs (outr, outf) that match the modulator rough and fine inputs (inr, inf). external anti-al ias series resistors and external differential c apacitors are required to create the anti-a lias rc filters. the approximate -3 db co rner of the input anti- alias filter is nominally set to the internal ana- log sampling rate divided by 64, which itself is a division by 4 of the mclk rate. figure 9 on page 14 illustrates the cs5371a and cs5372a modulator analog connections with input anti-alias filter components. filter com- ponents on the rou gh and fine pins should be identical values for opt imum performance, with the capacitor values a minimum of 0.02 f. the rough input can use either x7r- or c0g- type capacitors, while the fine input requires c0g-type capacitors for optimal linearity. us- ing x7r-type capacitors on the fine analog in- puts will significantly degrade total harmonic distortion performance. 4.4 analog differential signals differential analog signal s into the cs5371a and cs5372a consist of two halves with equal but opposite magnitude varying about a com- mon mode voltage. a full-scale, 5 v p-p , differ- ential signal centered on a -0.15 v common mode voltage will have: sig+ = -0.15 v + 1.25 v = +1.1 v sig- = -0.15 v - 1.25 v = -1.4 v sig+ is +2.5 v relative to sig- for the opposite case: sig+ = -0.15 v - 1.25 v = -1.4 v sig- = -0.15 v + 1.25 v = +1.1 v sig+ is -2.5 v relative to sig- so the total swing for sig+ relative to sig- is (+2.5 v) ? (-2.5 v) = 5 v p-p differential. a simi- lar calculation can be done for sig- relative to sig+. it?s important to note that a 5 v p-p differential signal centered on a -0.15 v common mode voltage never exceeds +1.1 v with respect to ground and never drops be low -1.4 v with re- spect to ground on either half. by definition, differential voltages ar e measured with re- spect to the opposite half, not relative to ground. a voltmeter differentially measuring between sig+ and sig- in the above example would correctly read 1.767 v rms , or 5 v p-p . ? mclk frequency = 2.048 mhz ? sampling frequency = mclk / 4 = 512 khz ? -3 db filter corner = sampling freq / 64 = 8 khz ? rc filter = 1 / [ 2 x(2xr series )xc diff ] ~ 8 khz
cs5371a cs5372a ds748f1 19 5. digital signals the cs5371a and cs5372a modulators are designed to operate with the cs5376a digital filter. the digital filt er generates the modulator clock and synchroniza tion signals (mclk and msync) while receiving back the modulator one-bit ? conversion data and over-range flag (mdata and mflag). 5.1 mclk connection the cs5376a digital fi lter generates the mas- ter clock for cs5371a and cs5372a, typically 2.048 mhz, from a sy nchronous clock input from the external system . if mclk is disabled during operation, the m odulators will enter a power down state after approximately 40 s. by default, mclk is disabled at reset and is enabled by writing the di gital filter config register. mclk must have low jitter to guarantee full an- alog performance, r equiring a crystal- or vcxo-based system clo ck input to the digital filter. clock jitter on the digital filter clk input directly translates to jitter on mclk. 5.2 msync connection the cs5376a digital filter also provides a syn- chronization signal to the cs5371a and cs5372a modulators. th e msync signal is automatically generat ed following a rising edge received on the digital filter sync input. by default, msync generation is disabled at reset and is enabled by writing the digital filter config register. the input sync signal to the cs5376a digital filter sets a common reference time t 0 for mea- surement events, thereby synchronizing ana- log sampling across a measurement network. the timing accuracy of the received sync sig- nal from measurement node to measurement node must be 1 mclk to maximize the cs5372a ? modulator inf+ inr+ inf- inr- inf- inr- inf+ inr+ vref+ vref- va+ va- vd gnd mdata1 mflag1 mdata2 mflag2 mclk msync pwdn1 ofst pwdn2 vref 2.5 v va+ va- 10 ? 0.01 f vd cs5376a digital filter vdd2 gnd mdata1 mflag1 mdata2 mflag2 mclk msync gpio gpio gpio va+ 0.1 f 0.01 f vd va- 0.1 f 20nf c0g 20nf c0g 680 cs3301a cs3302a amplifier outr+ outf+ outf- outr- 680 680 680 20nf c0g 20nf c0g 680 cs3301a cs3302a amplifier outr+ outf+ outf- outr- 680 680 680 va+ va+ va- va- va+ va+ va- va- 100 f figure 12. digital signals
cs5371a cs5372a 20 ds748f1 msync analog sample synchronization accu- racy. the cs5371a and cs 5372a msync input is rising-edge triggered and resets the internal mclk counter/divider to guarantee synchro- nous operation with ot her system devices. while the msyn c signal synchronizes the in- ternal operation of the modulators, by default, it does not synchronize the phase of the sine wave from the cs4373a test dac unless en- abled in the digital fi lter tbscfg register. 5.3 mdata connection during normal operation the cs5371a and cs5372a modulat ors output a ? serial bit stream to the mdata pi n, with a one?s density proportional to the diff erential amplitude of the analog input signal. the ou tput bit rate from the mdata output is a di vide-by-four of the in- put mclk, and so is nominally 512 khz. the mdata output has a 50% one?s density for a mid-scale anal og input, approximately 86% one?s density for a positive full-scale ana- log input, and approxim ately 14% one?s densi- ty for a negative full-sca le analog input. one?s density of the mdata output is defined as the ratio of ?1? bits to total bits in the serial bit stream output; i.e. an 86% one?s density has, on average, a ?1? value in 86 of every 100 out- put data bits. 5.4 mflag connection the cs5371a and cs5372a ? modulators have a fourth-order arch itecture which is con- ditionally stable and may go into an oscillatory condition if the analog inputs are over-ranged more than 5% past eit her positive or negative full-scale. when an unstable condition is detected, the modulator automatically co llapses to a first-or- der system to regain stability and then transi- tions the mflag output low-to-high to signal an error condition to the cs5376a digital filter. the mflag output connects to a dedicated in- put on the digital filter , causing an error flag to be set in the status byte of the next output data word. for the modulator to re cover from an unstable condition, the analog inpu t signal must be re- duced to within the full-s cale input range for at least 32 mclk cycles. if the analog input re- mains over-ranged for an extended period, the modulator will cycle between fourth-order and first-order operation and the mflag output will be seen to pulse. 5.5 ofst connection the cs5376a controls 12 general-purpose in- put output (gpio) pins through the digital filter gpcfg register. these gpio pins can be as- signed to operate the cs5371a and cs5372a ofst and pwdn pins. if the ofst pin is pulled high, idle tones are eliminated within the modulator by adding -60 mv (channel 1 of cs5371a and cs5372a) or -35 mv (channel 2 of cs5372a) of internal differential offset duri ng conversion to push idle tones out of the measurement bandwidth. care should be taken to ensure external offset voltages do not negate the internally added differential offset, or id le tones will re-appear.
cs5371a cs5372a ds748f1 21 6. power modes the cs5371a and cs5372a modulators have three power modes. no rmal operation, power down with mclk enab led, and power down with mclk disabled. 6.1 normal operation with mclk active and the pwdn pin driven low, the cs5371a and cs5372a modulators perform normal data acqui sition. a differential analog input signal is c onverted to an over- sampled 1-bit ? bit stream at 512 khz. this ? bit stream is then di gitally filt ered and deci- mated by the cs5376a device to a high-preci- sion 24-bit output. 6.2 power down, mclk enabled with mclk active and the pwdn pin driven high, the cs5371a and cs5372a modulators are placed into a powe r-down state. during this power-down state the modulators are dis- abled and all outputs are high impedance. 6.3 power down, mclk disabled if mclk is stopped, an internal loss-of-clock detection circuit automat ically places the cs5371a and cs5372a into a power-down state. this power-dow n state is independent of the pwdn pin setting and is automatically in- voked after approximately 40 s without re- ceiving an incoming mclk edge. during this power-down state, the modulators are disabled and all ou tputs are high imped- ance. when used with t he cs5376a digital fil- ter, the cs5371a and cs5372a are in this power-down state imm ediately after reset since mclk is disabled by default. normal operation mclk = on pwdn = 0 power down mclk = on pwdn = 1 power down mclk = off pwdn = x figure 13. power mode diagram
cs5371a cs5372a 22 ds748f1 7. voltage reference the cs5371a and cs5 372a modulators re- quire a 2.500 v precision voltage reference to be supplied to the vref pins. 7.1 vref power supply to guarantee proper r egulation headroom for the voltage reference dev ice, the voltage refer- ence gnd pin should be connected to va- in- stead of system ground, as shown in figure 14 . this connection results in a vref- voltage equal to va- and a vref+ voltage very near ground [(va-) + 2.500 vref]. power supply inputs to the voltage reference device should be bypassed to system ground with 0.1 f capacitors placed as close as pos- sible to the power and ground pins. in addition to 0.1 f local bypass capacitors, at least 100 f of bulk capacitance to system ground should be placed on each power supply near the voltage regulator outputs. bypass capaci- tors should be x7r, c0g, tantalum, or other high-quality dielectric type. 7.2 vref rc filter a primary concern in sele cting a precision volt- age reference device is noise performance in the measurement bandwidth. the linear technology lt1019ais8-2.5 voltage refer- ence yields acceptable noi se levels if the out- put is filtered with a low-pass rc filter. a separate rc filter is required for each sys- tem device connected to a given voltage refer- ence output. by sharing a common rc filter, signal-dependent sampling of the voltage ref- erence by one system devi ce could cause un- wanted tones to appear in the measurement bandwidth of another system device via com- mon impedance coupling. 7.3 vref pcb routing to minimize the possibility of outside noise coupling into the cs 5371a and cs5372a volt- age reference input, the vref traces should be routed as a differential pair from the large capacitor of the voltage reference rc filter. careful control of the voltage reference source and return currents by routing vref as a dif- ferential pair will signifi cantly improve immuni- ty from external noise. to further improve noi se rejection of the vref differential route, include 0.1 f by- pass capacitors to system ground as close as possible to the vref+ and vref- pins of the cs5371a and cs5372a. 7.4 vref input impedance the switched-capacitor input architecture of the vref inputs results in an input imped- ance that depends on the internal capacitor size and the mclk frequen cy. with a 15 pf in- ternal capacitor and a 2.048 mhz mclk, the vref input impedance is approximately 1 / [(2.048 mhz) x (15 pf)] = 32 k ? . while the size of the internal capac itor is fix ed, the volt- 10 ? to vref+ + from va+ regulator 2.500 v vref 0.1 f to vref- 0.1 f 100 f 0.1 f 0.1 f 0.1 f 100 f 100 f from va- regulator route vref as a differential pair from the 100uf rc filter capacitor figure 14. voltage reference circuit
cs5371a cs5372a ds748f1 23 age reference input impedance will vary with mclk. the voltage reference exte rnal rc filter series resistor creates a vo ltage divider with the vref input impedance to reduce the effective applied input voltage. to minimize gain error resulting from this volt age divider effect, the rc filter series resist or should be the minimum size recommended in the voltage reference device data sheet. 7.5 vref accuracy the nominal voltage refe rence input is speci- fied as 2.500 v across the vref pins, and all cs5371a and cs5372a gai n accuracy speci- fications are measured using a nominal volt- age reference input. an y variation from a nominal vref input will proportionally vary the analog full-scale gain accuracy. since temperature drift of the voltage refer- ence results in gain drift of the analog full-scale amplitude, care should be taken to minimize temperature drift effects through careful selec- tion of passive components and the voltage reference device itself. gain drift specifications of the cs5371a and cs5372a do not include the temperature drift effects of external pas- sive components or of the voltage reference device itself.
cs5371a cs5372a 24 ds748f1 8. power supplies the cs5371a and cs5372a modulators have a positive analog power supply pin (va+), a negative analog power suppl y pin (va-), a dig- ital power supply pin (vd), and a ground pin (gnd). for proper operation, power must be supplied to all power supply pi ns, and the ground pin must be connected to system ground. the cs5371a and cs5372a di gital power supply (vd) and the cs5376a di gital power supply (vdd) must share a common voltage. 8.1 power supply bypassing the va+, va-, and vd power supplies should be bypassed to system ground with 0.1 f ca- pacitors placed as close as possible to the power pins of the devi ce. in addition to the 0.1 f local bypass capacit ors, at least 100 f bulk capacitance to system ground should be placed on each power supply near the voltage regulator output, with additional power supply bulk capacitance placed among the analog component route if space permits. bypass ca- pacitors should be x7r, c0g, tantalum, or other high-quality dielectric type. 8.2 pcb layers and routing the cs5371a and cs5372a are high-perfor- mance devices, and spec ial care must be tak- en to ensure power and ground routing is correct. power can be supplied either through dedicated power planes or routed traces. when routing power trac es, it is recommended to use a ?star? routing scheme with the star point either at the volt age regulator output or at a local power supply bulk capacitor. it is also recommended to dedicate a full pcb layer to a solid ground plane, without splits or routing. all bypass capac itors should connect between the power suppl y circuit and the solid ground plane as near as possible to the device power supply pins. the cs5371a and cs5372a analog signals are differentially routed and do not normally re- quire connection to a separate analog ground. however, if a separat e analog ground is re- quired, it should be ro uted using a ?star? rout- ing scheme on a separate layer from the solid ground plane and connec ted to the ground plane only at a single point. be sure all active devices and passive components connected to the separate analog ground are included in the ?star? route to ensure sensitive analog cur- rents do not return th rough the ground plane. 8.3 power supply rejection power supply rejection of the cs5371a and cs5372a is frequen cy dependent. the cs5376a digital filter fu lly rejects power sup- ply noise for frequencie s above the selected digital filter corner frequency. power supply noise frequencies between dc and the digital filter corner frequency ar e rejected as speci- fied in the power supply characteristics table. cs5371a cs5372a va+ vd va- gnd 0.1 uf 100 uf 0.1 uf 100 uf 100 uf 0.1 uf to va+ regulator to va- regulator to vd regulator figure 15. power supply diagram
cs5371a cs5372a ds748f1 25 8.4 scr latch-up considerations it is recommended to connect the va- power supply to system grou nd (gnd) with a re- verse-biased schottky diode. at power up, if the va+ power supply ramps up before the va- supply is establishe d, the va- pin voltage could be pulled abov e ground potential through the cs5371a and cs5372a device. if the va- supply is pull ed 0.7 v or more above gnd, scr latch-up can occur. a reverse-bi- ased schottky diode will clamp the va- voltage a maximum of 0.3 v above ground to ensure scr latch-up does not occur at power up. 8.5 dc-dc converters many low-frequency measurement systems are battery powered and utilize dc-dc con- verters to efficiently generate power supply voltages. to minimize interference effects, op- erate the dc-dc converter at a frequency which is rejected by the digital filter , or operate it synchronous to the mclk rate. a synchronous dc-dc converter whose oper- ating frequency is derive d from mclk will the- oretically minimize th e potential for ?beat frequencies? to appear in the measurement bandwidth. however this requires the source clock to remain jitter free within the dc-dc converter circuitry. if clo ck jitter can occur with- in the dc-dc converter (as in a pll-based ar- chitecture), it?s be tter to use a non- synchronous dc-dc converter whose switch- ing frequency is rejected by the digital filter. during pcb layout, do not place high-current dc-dc converters near sensitive analog com- ponents. carefully rout ing a separate dc-dc ?star? ground will help isolate noisy switching currents away from the sensitive analog com- ponents.
cs5371a cs5372a 26 ds748f1 9. pin description - cs5371a power supplies va+ _ positive analog power supply, pin 8 va- _ negative analog power supply, pin 7 vd _ positive digital power supply, pin 13, 18 gnd _ ground, pin 17, 23 analog inputs inr+ _ rough non-inverting input, pin 1 rough non-inverting analog input. the rough input settles non-linear currents to improve linearity on the fine input and reduce harmonic distortion. inf+ _ fine non-inverting input, pin 2 fine non-inverting analog input. inf- _ fine inverting input, pin 3 fine inverting analog input. inr- _ rough inverting input, pin 4 rough inverting analog input. the rough input settles non-linear currents to improve linearity on the fine input and reduce harmonic distortion. 1 2 3 4 5 6 7 817 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 rough non-inverting input inr+ fine non-inverting input inf+ fine inverting input inf- rough inverting input inr- positive voltage reference input vref+ negative voltage reference input vref- negative analog power supply va- positive analog power supply va+ no internal connection nc no internal connection nc no internal connection nc no internal connection nc pwdn power-down enable gnd digital ground mflag modulator flag output mdata modulator data output msync modulator sync input mclk modulator clock input vd positive digital power supply gnd digital ground nc no internal connection nc no internal connection ofst offset mode select vd positive digital power supply
cs5371a cs5372a ds748f1 27 vref+ _ positive voltage re ference input, pin 5 input for an external +2.500 v voltage reference relative to vref-. vref- _ negative voltage refe rence input, pin 6 this pin should be tied to va- near the voltage reference output. digital inputs mclk _ modulator clock input, pin 19 a cmos compatible clock input for the modulator internal master clock, nominally 2.048 mhz with an amplitude equal to the vd digital power supply. msync _ modulator sync input, pin 20 a low to high transition resets the internal cl ock phasing of the modulator. this assures the sampling instant and modulator data output are synchronous to the external system. ofst _ offset mode select, pin 14 when high, adds approximately -60 mv or -35 mv of internal differential offset to the analog input signal to guarantee any ? idle tones are removed. when low, no offset is added. pwdn _ power-down mode, pin 24 when high, the modulator is in power-down mode. halting mclk while in power down mode reduces modulator power dissipation further. digital outputs mdata _ modulator data output, pin 21 modulator data is output as a 1-bit serial da ta stream at 512 khz with an mclk input of 2.048 mhz. mflag _ modulator flag output, pin 22 a high level output indicates the modulator is unstable due to an over-range on the analog inputs.
cs5371a cs5372a 28 ds748f1 10. pin description - cs5372a power supplies va+ _ positive analog power supply, pin 8 va- _ negative analog power supply, pin 7 vd _ positive digital power supply, pin 18 gnd _ ground, pin 17, 23 analog inputs inr1+, inr2+ _ channel 1 & 2 rough non-inverting inputs, pin 1, 12 rough non-inverting analog inputs. the rough i nputs settle non-linear currents to improve linearity on the fine inputs and reduce harmonic distortion. inf1+, inf2+ _ channel 1 & 2 fine non-in verting input, pin 2, 11 fine non-inverting analog inputs. inf1-, inf2- _ channel 1 & 2 fine inver ting input, pin 3, 10 fine inverting analog inputs. inr1-, inr2- _ channel 1 & 2 rough invert ing inputs, pin 4, 9 rough inverting analog inputs. the rough inputs settle non-linear currents to improve linearity on the fine inputs and reduce harmonic distortion. 1 2 3 4 5 6 7 817 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 ch. 1 rough non-inverting input inr1+ ch. 1 fine non-inverting input inf1+ ch. 1 fine inverting input inf1- ch. 1 rough inverting input inr1- positive voltage reference input vref+ negative voltage reference input vref- negative analog power supply va- positive analog power supply va+ ch. 2 rough inverting input inr2- ch. 2 fine inverting input inf2- ch. 2 fine non-inverting input inf2+ ch. 2 rough non-inverting input inr2+ pwdn1 ch. 1 power-down enable gnd digital ground mflag1 ch. 1 modulator flag output mdata1 ch. 1 modulator data output msync modulator sync input mclk modulator clock input vd positive digital power supply gnd digital ground mdata2 ch. 2 modulator data output mflag2 ch. 2 modulator flag output ofst offset mode select pwdn2 ch. 2 power-down enable
cs5371a cs5372a ds748f1 29 vref+ _ positive voltage re ference input, pin 5 input for an external +2.5 v voltage reference relative to vref-. vref- _ negative voltage refe rence input, pin 6 this pin should be tied to va- near the voltage reference output. digital inputs mclk _ modulator clock input, pin 19 a cmos compatible clock input for the modulator internal master clock, nominally 2.048 mhz with an amplitude equal to the vd digital power supply. msync _ modulator sync input, pin 20 a low to high transition resets the internal cl ock phasing of the modulator. this assures the sampling instant and modulator data output are synchronous to the external system. ofst _ offset mode select, pin 14 when high, adds approximately -60 mv or -35 mv of internal differential offset to the analog input signal to guarantee any ? idle tones are removed. when low, no offset is added. pwdn1, pwdn2 _ channel 1 & 2 power- down mode, pin 24, 13 when high, the modulator is in power down mode. halting mclk while in power down mode reduces modulator power dissipation further. digital outputs mdata1, mdata2 _ modulator data output, pin 21, 16 modulator data is output as a 1-bit serial da ta stream at 512 khz with an mclk input of 2.048 mhz. mflag1, mflag2 _ modulator flag, pin 22, 15 a high level output indicates the modulator is unstable due to an over-range on the analog inputs.
cs5371a cs5372a 30 ds748f1 11. package dimensions notes: 1. ?d? and ?e1? are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. dimension ?b? does not include dambar protrusion /intrusion. allowable dambar protrusion shall be 0.13 mm total in excess of ?b? dimension at maximu m material condition. dambar intrusion shall not reduce dimension ?b? by more than 0.07 mm at least material condition. 3. these dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. inches millimeters note dim min max min max a -- 0.084 -- 2.13 a1 0.002 0.010 0.05 0.25 a2 0.064 0.074 1.62 1.88 b 0.009 0.015 0.22 0.38 2,3 d 0.311 0.335 7.90 8.50 1 e 0.291 0.323 7.40 8.20 e1 0.197 0.220 5.00 5.60 1 e 0.024 0.027 0.61 0.69 l 0.025 0.040 0.63 1.03 0 8 0 8 24 pin ssop package drawing e n 1 23 e b 2 a1 a2 a d seating plane e1 1 l side view end view top view
cs5371a cs5372a ds748f1 31 12. ordering information 13.environmental, manufacturi ng, & handling information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. model temperature package cs5371a-isz (lead free) -40 to +85 c 24-pin ssop CS5372A-ISZ (lead free) model number peak reflow temp msl rating* max floor life cs5371a-isz (lead free) 260 c 3 7 days CS5372A-ISZ (lead free)
cs5371a cs5372a 32 ds748f1 14.revision history revision date changes pp1 oct 2006 preliminary release. f1 dec 2006 updated to final status with most-rec ent characterization data for cirrus qpl pro- cess. contacting cirrus logic support for all product questions and inquiries contac t a cirrus logic sales representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries ("cirrus") believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided "as is" without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those per taining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use with in your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor pr oducts may involve potential risks of death, personal injury, or severe prop- erty or environmental damage ("critical applications"). cir rus products are not designed, au thorized or warranted for use in aircraft systems, milita ry applications, products surgically implanted in to the body, automotive safety or security de- vices, life support produc ts or other critical applic ations. inclusion of cirrus products in such applicat ions is understood to be fully at the customer's risk and cirrus disclaims and make s no warranty, express, statutory or implied, including the implied warranties of merchantability and fitness for particular purp ose, with regard to any cirrus product that is used in such a manner. if the customer or cu stomer's customer uses or permits the use of cirrus products in critical applica- tions, customer agrees, by such use, to fully indemnify cir rus, its officers, directors, em ployees, distributors and other agents from any and all liability, including attorneys' fees a nd costs, that may result from or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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